1. Field of the Invention
The present invention relates to a semiconductor memory device and, more specifically, to a structure of a portion generating a test mode activating signal for placing the semiconductor memory device in a test mode. More specifically, the present invention relates to a structure for initializing the test mode activating signal generating portion at the time of power on.
2. Description of the Background Art
In semiconductor memory devices such as synchronous semiconductor memory devices, various tests are performed to ensure reliability of the products. Such tests include a screening test for revealing latent defects and screening out a defective product having initial failure at the time of marketing, and a multibit test mode for testing a plural bits of memory cells simultaneously for detecting absence/presence of defects of memory cells in a short period of time. The screening test has a burn in mode in which a semiconductor memory device is operated under a condition of higher temperature and higher voltage than the normal operating condition. These test modes are operation modes performed before marketing of the products, and these test modes are not utilized in a system which is actually used by a user.
When the semiconductor memory device enters a test mode in a system in which the semiconductor memory device is actually used, the internal state of the semiconductor memory device changes from the state in a normal operation mode, possibly causing malfunction. In order to prevent the semiconductor memory device from entering the test mode in actual use, generally, the test mode is set by a combination of states of a plurality of external signals which is not used in the normal operation mode in actual use. However, there are nodes of which initial output voltage cannot be determined in advance such as those in a latch circuit or a flipflop, or internal nodes which are floating, in the internal circuitry at the time of power on (at the start of application of power supply voltage to the semiconductor memory device). Therefore, the voltages of these internal nodes are non-predictable at the time of power on. In this case, if a timing condition allowing entrance to the test mode is met because of the voltage level of those nodes of which voltage levels are non-predictable (that is, of which voltage levels cannot be determined in advance after power on), the semiconductor memory device may possibly enter the test mode. In order to surely reset the non-predictable voltage levels of the internal nodes, a power on detection signal POR is used for resetting the non-predictable node(s) to a prescribed voltage level at the time of power on.
FIG. 13 schematically shows a structure of a conventional test mode activating signal generating circuit. Referring to FIG. 13, a test mode activating signal generating circuit 100 includes a tristate inverter buffer 100a which is enabled when mode set instructing signals MSET and ZMSET are activated, for inverting an externally applied specific address signal bit Add, buffering and transmitting it to an internal node NA, and a test mode activating signal output circuit 100b for outputting a test mode activating signal TME in accordance with the voltage of internal node NA and for latching the test mode activating signal TME when mode set instructing signals MSET and ZMSET are activated. Tristate inverter buffer 100a is set to an output high impedance state when mode set instructing signals MSET and ZMSET are inactivated.
Test mode activating signal output circuit 100b includes an inverter 100ba for inverting a signal on node NA for transmission to a node NB to generate test mode activating signal TME, and a tristate inverter buffer 100bb which is activated when mode set instruction signals MSET and ZMSET are activated, for transmitting a signal on node NB to node NA. Tristate inverter buffer 100bb is also set to an output high impedance state when mode set instructing signals MSET and ZMSET are inactivated.
Test mode activating signal generating circuit 100 further includes a p channel MOS transistor 102 responsive to activation of power on detection signal ZPOR for electrically connecting a power supply node NV to internal node NA. Power on detection signal ZPOR is kept at an active state of L level until the power supply voltage Vcc is applied to power supply node NV and voltage level at the node NV attains to a prescribed voltage level or attains to a stable state.
Operation of test mode activating signal generating circuit 100 shown in FIG. 13 will be described with reference to FIG. 14, which is a timing chart thereof.
In a synchronous semiconductor memory device, an operation mode is designated by a combination of states of external signals at a rise of a clock signal CLK. In a clock cycle #a, at a rising edge of clock signal CLK, row address strobe signal ZRAS, column address strobe signal ZCAS and write enable signal ZWE are all set to the L level. This state is referred to as a mode set command, which designates a mode different from the normal operation mode. When the mode set command is applied, a specific address signal bit Add is set to the H level.
When the mode set command is applied, mode set instructing signal MSET is set to and kept at the H level for a prescribed time period, and tristate inverter buffer 100a shown in FIG. 13 operates so that address signal bit Add is inverted and transmitted to internal node NA. The signal transmitted to internal node NA is inverted and transmitted to internal node NB by inverter circuit 100ba, and test mode activating signal TME attains to the H level. In test mode activating signal generating circuit 100b, tristate inverter buffer 100bb operates complementarily to tristate inverter buffer 100a, so that when mode set instructing signal MSET attains to the inactive state of L level, tristate inverter buffer 100bb is set to an operative state, and thus inverter 100ba and tristate inverter buffer 100bb constitute a latch circuit. Test mode activating signal TME is held at the active state of H level.
When test mode activating signal TME is set to the active state of H level in clock cycle #a, the semiconductor memory device enters the test mode (test mode entry). Thereafter, from the next clock cycle #b, a prescribed test operation is performed (test cycle period). In the test cycle period, tristate inverter buffer 100a is at an output high impedance state, tristate inverter buffer 100bb operates as an inverter, and therefore test mode activating signal TME is held at the H level.
When the test operation activated by the test mode activating signal TME is completed in clock cycle #c, the mode set command is again applied in clock cycle #d, and the mode set instructing signal MSET attains to and kept at the H level for a prescribed time period. Tristate inverter buffer 100a is set to an operative state, while tristate inverter buffer 100bb is set to the output high impedance state. Consequently, a signal at the H level is transmitted to internal node NA and, in response, test mode activating signal TME attains to the inactive state of L level. When mode set instructing signal MSET falls to the L level, tristate inverter buffer 100a attains to the output high impedance state, tristate inverter buffer 100bb is set to the operative state and the test mode activating signal TME is held at the L level. Consequently, the test mode is reset and thereafter, operation of another mode is performed.
The above described operation takes place when power supply voltage Vcc is turned on and the power supply voltage Vcc attains a stable state. The operation of test mode activating signal generating circuit 100 at the time of power on will be described.
At the time of power on, tristate inverter buffer 100a is at the output high impedance state, and test mode activating signal generating circuit 100b constitutes a latch circuit. In this state, voltage level of internal node NA in the initial state is determined by the state of the latch circuit (inverter 100ba and tristate inverter buffer 100bb) at the time of power on.
Now, when power supply voltage is turned on at time t0 as shown in FIG. 15, the power supply voltage Vcc on node NV rises gradually. The latch state of test mode activating signal generating circuit 100b is not predictable at the time of power on, and therefore the voltage levels of internal node NA and test mode activating signal TME are not predictable either (in FIG. 15, the voltage levels are shown as gradually rising, by dotted lines). This is because inverter 100ba and tristate inverter buffer 100bb are both in transient region in the initial state, consuming through current, so that output voltage levels thereof are non-predictable.
Until the power supply voltage Vcc attains to a prescribed voltage level at time t1, power on detection signal ZPOR is kept at L level, p channel MOS transistor 102 is rendered conductive in response, and internal node NA is electrically connected to power supply node NV. By the conduction of MOS transistor 102, the voltage level of internal node NA is set to the H level, initial state of the latch state of the test mode activating signal generating circuit 100b is set, internal node NA attains to the H level and internal node NB attains to the L level.
At time t1, even when power on detection signal ZPOR rises to the H level and MOS transistor 102 is rendered non-conductive, voltage levels of internal nodes NA and NB vary because of the latch circuit including inverter 100ba and tristate inverter buffer 100bb, such that internal node NA rises to the H level as the voltage level of power supply voltage Vcc increases, while test mode activating signal TME from node NB falls to the L level as the voltage level of internal node NA rises. Consequently, when the power supply voltage Vcc finally attains to the prescribed voltage level Va, internal node NA attains to the H level corresponding to the level of voltage Va, and test mode activating signal TME is held at the L level which corresponds to the ground level of the ground voltage GND. At the time of power on, the test mode activating signal generating circuit can be reset to a desired initial state, and hence erroneous activation of test mode activating signal TME at the time of power on can be prevented.
FIG. 16 shows an example of a conventional power on detection circuit. Referring to FIG. 16, the power on detection circuit includes a p channel MOS transistor P1 connected between a node S1 and a power supply node NV and having a gate connected to a node S2; a resistance element Z1 having one end connected to node S1; an n channel MOS transistor Q1 connected between the other end of resistance element Z1 and a ground node and having a gate connected to node S2; a coupling capacitance CP1 connected between power supply node NV and node S1; an n channel MOS transistor Q2 connected between node S2 and ground node and having a gate connected to node S1; and a p channel MOS transistor P2 and a resistance element Z2 connected in series between power supply node NV and node S2. The gate of p channel MOS transistor P2 is connected to node S1. A capacitance element CP2 is further provided for stabilizing the voltage level of node S2, between node S2 and the ground node.
The power on detection circuit further includes three stages of cascaded inverters IV1, IV2 and IV3 for receiving and inverting a signal on node S2 for transmission to node S3, a coupling capacitance CP3 connected between node S3 and power supply node NV; an inverter IV4 inverting a signal potential on node S3 for transmission to node S4; and two stages of cascaded inverters IV5 and IV6 for outputting power on detection signal ZPOR in accordance with a signal potential on node S4.
The power on detection circuit further includes a p channel MOS transistor P3 and a resistance element Z3 connected in series between power supply node NV and a node S5. The gate of p channel MOS transistor P3 is connected to node S4.
The power on detection circuit further includes an n channel MOS transistor Q3 connected between node S5 and the ground node and having a gate connected to node S4; a capacitance element CP4 connected between node S5 and the ground node; p channel MOS transistors P4 and P5 connected in series between nodes S5 and S6; an n channel MOS transistor Q4 connected between node S6 and the ground node and having a gate connected to node S4; and an n channel MOS transistor Q5 connected between node S1 and the ground node and having a gate connected to node S6. Each of p channel MOS transistors P4 and P5 has its gate and drain connected, and functions as a voltage lowering element. Operation of the power on detection circuit shown in FIG. 16 will be described with reference to the diagrams of operational waveforms of FIGS. 17 and 18.
Referring to FIG. 17, operation when power on detection signal ZPOR is generated normally will be described. Power is turned on at time t0, and the voltage level of power supply voltage Vcc at power supply node NV rises. As the power is turned on, because of capacitive coupling of capacitance element CP1, the voltage level of node S1 rises in response, n channel MOS transistor Q2 is rendered conductive, and p channel MOS transistor P2 is rendered non-conductive. As n channel MOS transistor Q2 is rendered conductive, node S2 is held at the level of the ground voltage. Consequently, by inverters IV1 to IV3, the voltage level of node S3 rises to the H level in accordance with the level of the power supply voltage. Node S3 has its voltage level reset at the H level at the time of power on because of capacitive coupling of capacitance element CP3, and accordingly, the signal level output to node S4 is set to the L level by inverter IV4, and power on detection signal ZPOR is held at the L level.
While the node S4 is at the L level, p channel MOS transistor P3 is conductive, and in accordance with a time constant defined by resistance element Z3 and capacitance element CP4, the voltage level of node S5 rises moderately. When the voltage level of node S5 exceeds threshold voltages of MOS transistors P4 and P5, the voltage of node S6 begins to rise. When the voltage level of node S6 becomes higher than the threshold voltage of MOS transistor Q5, MOS transistor Q5 is rendered conductive and node S1 is discharged to the L level.
As the voltage level at node S1 lowers, p channel MOS transistor P2 is rendered conductive, and voltage level at node S2 rises in accordance with a time constant determined by resistance element Z2 and capacitance element CP2. As the voltage level of node S2 rises, p channel MOS transistor P1 is rendered non-conductive, and the voltage level of node S1 is surely discharged to the L level. As the voltage level of node S1 lowers, MOS transistor Q2 is rendered non-conductive, and node S2 rises to the H level as the voltage level of power supply voltage Vcc rises. When the voltage level of node S2 exceeds an input logic threshold voltage of inverter IV1, node S3 is discharged and the voltage level thereat is lowered, and in response, the voltage level of node S4 rises. As the level of node S4 rises, power on detection signal ZPOR rises to the H level.
When the voltage level of node S4 rises, p channel MOS transistor P3 is rendered non-conductive, n channel MOS transistors Q3 and Q4 are rendered conductive, nodes S5 and S6 are discharged to the level of the ground voltage and MOS transistor Q5 is rendered non-conductive. As a result, as the voltage level of node S2 rises, MOS transistor Q1 is rendered conductive, and node S1 is held at the L level. By a loop of MOS transistors P2, Q1 and resistance elements Z1 and Z2, node S2 is held at the H level which corresponds to the voltage level of power supply voltage Vcc and, in response, power on detection signal ZPOR is also held at the H level.
From time point t0 when the power is turned on to the time point t1 when power on detection signal ZPOR rises to the H level, power on detection signal ZPOR is at the L level and in this period, internal nodes are reset. More specifically, power on detection signal ZPOR is set to the inactive state of H level when the power supply voltage Vcc attains a prescribed voltage level or a certain voltage level and becomes stable.
Referring to FIG. 18, operation when power on detection signal ZPOR is output imperfectly (with no active state) will be described.
As shown in FIG. 18, power is turned on at time t0 and the voltage level of power supply voltage Vcc increases. The speed of increase of the voltage level of power supply voltage Vcc is moderate. In this case, voltage levels of nodes S1 to S6 are not-defined. Conduction/non-conduction of MOS transistors are not established, speed of increase of voltage levels derived from capacitive coupling of capacitance elements CP1 and CP3 are quite moderate, and internal nodes are not able to shift voltage levels from the undetermined state to the established state. Therefore, in this state, when the voltage level, which is not predictable and non-defined, of internal node S4 is determined to be at the H level, power on detection signal ZPOR output through inverters IV5 and IV6 has its level increased as the voltage level of power supply voltage Vcc increases. When the voltage level of power supply voltage Vcc attains to a prescribed voltage level, voltage levels of those of internal nodes S1 to S6 which have attained to the H level surely increase, and nodes S1 to S6 are driven to prescribed voltage levels respectively.
The voltage level to which each node is driven is determined by the state of conduction/non-conduction of the MOS transistors. In FIG. 18, an operation sequence in which MOS transistor Q1 discharges node S1 to the level of the ground potential as the voltage of node S2 increases, is shown as an example. In this state, node S2 is charged through MOS transistor P2, its voltage level increases to the H level, node S3 is driven to the L level in response, and the voltage of node S4 is driven to the H level. When node S4 is driven to the H level, nodes S5 and S6 are also driven to L level.
Accordingly, in the operation sequence shown in FIG. 18, power on detection signal ZPOR has its voltage level increased in synchronization with the power supply voltage Vcc. Therefore, there is not a period in which power on detection signal ZPOR is held at the L level, and therefore reset operation for holding internal non-predictable nodes at prescribed initial voltages level is impossible.
When the speed of rise of power supply voltage Vcc is slow and power on detection signal ZPOR is generated imperfectly as shown in FIG. 18, the following problem arises.
More specifically, referring to FIG. 19, power is turned on at time t0, and in response, voltage level of power on detection signal ZPOR increases. Meanwhile, nodes NA and NB shown in FIG. 13 have the voltage levels not predictable in the initial state, and the voltage levels are determined by the state of latching of test mode activating signal generating circuit 100b. Therefore, when power on detection signal ZPOR has the voltage level thereof increased in accordance with the power supply voltage Vcc, then MOS transistor 102 is non-conductive and whether the voltage levels of nodes NA and NB assume H level or L level is determined dependent on the voltage levels of nodes NA and NB at that time. Therefore, when the power supply voltage Vcc attains to a prescribed voltage level or higher and the latch circuit of test mode activating signal generating circuit 100b enters the latch state, there are two states, i.e., one in which the signal at node NA attains to the H level and the signal at node NB, that is, test mode activating signal TME attains to the L level, and another in which the voltage level at node NA attains to the L level and test mode activating signal TME attains to the H level.
The test mode activating signal TME at the H level means that test mode is to be performed in the semiconductor memory device, and in normal operation mode, there is a possibility of malfunction.
In a standard DRAM (Dynamic Random Access Memory), a dummy cycle is provided for setting internal signal lines and internal nodes to prescribed initial states. However, what is done in the dummy cycle is simply to toggle the row address strobe signal/RAS several times, which means that only RAS related circuitry (circuitry related to the signal RAS, including circuits related to row selection) operates, and peripheral circuitry including the test mode activating signal generating portion is not reset.
In an SDRAM (Synchronous DRAM), a normal mode set cycle is performed in which special operation modes other than the normal operation mode (operation mode for data reading/writing) are all reset. If such a special normal mode set cycle is prepared, it is possible to reset the erroneously set test mode activating signal TME to the initial state. However, one of the test modes in which operation margin and operation characteristics are tested by externally applying a bias voltage VBB to a semiconductor substrate region, which is referred to as VBB application mode, cannot be reset even by the normal mode set cycle.
FIG. 20 schematically shows a circuit structure for performing VBB application mode. Referring to FIG. 20, the circuit for implementing VBB application mode includes VBB generating circuit 120 which is set to an operative state when test mode activating signal TME is inactive, for generating a bias voltage of a prescribed voltage level, and a selector 122 for selecting bias voltage from VBB generating circuit or an external voltage Ex applied from an external terminal 121 in accordance with test mode activating signal TME. The voltage from selector 122 is applied to a substrate region 123 of the semiconductor memory device. Substrate region 123 is a P type semiconductor substrate region and at the surface of substrate region 123, N type impurity regions 124a and 124b having high concentration are formed apart from each other. Between impurity regions 124a and 124b, a gate electrode layer 125 is formed with a gate insulating film underlaid. Thus one MOS transistor is provided in FIG. 20.
Generally, the substrate region 123 is formed of a well region or an epitaxial layer and a negative bias voltage is applied thereto.
When test mode activating signal TME is inactive, selector 122 selects and applies to substrate region 123 the bias voltage generated by VBB generating circuit 120. When test mode activating signal TME is active, selector 122 selects and applies to substrate region 123, the external voltage Ex applied from external terminal 121. Substrate bias voltage VBB stabilizes threshold voltage of the MOS transistor formed at the surface of the substrate region (transistor consisting of impurity regions 124a and 124b and gate electrode layer 125), and realizes high speed operation by reducing junction capacitance between substrate region 123 and impurity regions 124a and 124b.
The threshold voltage of the MOS transistor is represented as a function of a root of an absolute value of substrate bias voltage VBB. When the absolute value of bias voltage VBB increases, the threshold voltage of the MOS transistor increases. When the absolute value of the bias voltage VBB becomes smaller, the threshold voltage of the MOS transistor becomes smaller.
At the surface of substrate region 123, MOS transistors constituting the semiconductor memory device are formed. At the time of power on, when test mode activating signal TME is activated, selector 122 selects the external voltage Ex at external terminal 121. To external terminal 121, an external control signal (for example, row address strobe signal ZRAS or a column address strobe signal ZCAS) is applied in the normal operation mode. Therefore, at the time of power on, the external voltage Ex is at the ground voltage level or at the voltage level of the power supply voltage Vcc. When the external voltage Ex at the level of the ground voltage is selected and applied to substrate region 123, the threshold voltage of the MOS transistor becomes smaller and the MOS transistor, which is to be off, turns on. Therefore, even if normal mode set cycle is performed in the synchronous semiconductor memory device, internal nodes and internal signal lines cannot be set to the prescribed initial voltage levels as the transistor characteristic is different (which means that internal circuitry does not operate normally but malfunctions), and therefore data cannot be written or read correctly. There is also a possibility that a command decoder for decoding the externally applied normal mode set command does not operate normally, output of the normal mode set signal fails and, eventually, internal resetting is impossible.
When the external voltage Ex of external terminal 121 shown in FIG. 20 is set at the H level, the voltage level corresponds to the level of the power supply voltage Vcc. Therefore, when one of the impurity regions 124a and 124b is connected to the ground node, the substrate region 123 and the impurity region 124a or 124b is biased in forward direction, a large substrate current flows from external terminal 121 through selector 122, substrate region 123 and impurity region 124a or 124b, a larger current flows at a portion, not shown, by a latch up phenomenon caused by the large substrate current, and the semiconductor memory device may possibly run away. Further, it is possible that the large current causes disconnection of a line by heat (electromigration), eventually destroying the memory device.